New metal fill considerations for nanometer technologies

The use of metal fill insertion to create a uniform interconnect layout pattern that minimizes topographical variation is a widely adopted practice for nanometer technologies. This paper presents new advances and considerations to achieve maximum metal density uniformity while minimizing impact on chip timing by using timing aware methods. It also describes a full comprehensive metal fill methodology which includes metal fill insertion, metal fill trimming and metal density verification. Finally some new customer requested features such as staggered pattern metal fill and power strapping are also described