A low power 128-tap digital adaptive equalizer for broadband modems

This chip provides programmable fractional spacings and slicers making it suitable for 51Mb/s and 155Mb/s ATM over CAT3, as well as for the emerging 100Mb/s base-T2 fast Ethernet standard. The primary design goal is to minimize the power consumption so that the equalizer may be integrated into low-cost single-chip transceivers. Two 64-tap adaptive FIR filters are configured in parallel as in-phase and quadrature filters. Each has a span of l6T, where T is the symbol period, and is programmable to operate with T/2, T/3 or T/4 fractional spacing. On-chip programmable slicers enable slicing of up to 8x8 constellations. They use a reduced constellation for blind training and switch to the full constellation to obtain final convergence. The filters feature a zero latency cascadable systolic FIR structure that has the low power advantages of the direct form due to the reduced number of flip-flops in the output path, as well as the reduced critical path advantages of the transposed form. A programmable delay synchronizes the input data with the coefficients and the error for correct least mean squares (LMS) coefficient adaption with different fractional spacings.