• DocumentCode
    3470446
  • Title

    Iterative Refinement on FPGAs

  • Author

    Jun Kyu Lee ; Peterson, Gregory D.

  • Author_Institution
    Electr. Eng. & Comput. Sci., Univ. of Tennessee, Knoxville, TN, USA
  • fYear
    2011
  • fDate
    19-21 July 2011
  • Firstpage
    8
  • Lastpage
    13
  • Abstract
    Achievable accuracy for mixed precision iterative refinement depends on the precisions supported by computing platforms. Even though the arithmetic unit precision can be flexible for programmable logic computing architectures (e.g. FPGAs), previous work rarely discusses the performance benefits due to enabling flexible achievable accuracy. Hence, we propose an iterative refinement approach on FPGAs which employs an arbitrary precision for the iterative refinement to obtain an arbitrary accuracy. We implement single processing elements for the refinement on the Xilinx XC5VLX110T and compare them to Xilinx XC6VSX475T for performance estimation. This paper shows that the performance is similar to the NVIDIA GTX480 when a user requires accuracies between single and double precision, but the implementation can also produce beyond double precision accuracy.
  • Keywords
    field programmable gate arrays; iterative methods; FPGA; NVIDIA GTX480; Xilinx XC5VLX110T; arithmetic unit; iterative refinement; programmable logic computing architectures; Accuracy; Adders; Approximation methods; Clocks; Convergence; Field programmable gate arrays; Pipelines; FPGAs; High performance; Linear systems; Mixed precision iterative refinement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Application Accelerators in High-Performance Computing (SAAHPC), 2011 Symposium on
  • Conference_Location
    Knoxville, TN
  • Print_ISBN
    978-1-4577-0635-6
  • Electronic_ISBN
    978-0-7695-4448-9
  • Type

    conf

  • DOI
    10.1109/SAAHPC.2011.19
  • Filename
    6031558