High bandwidth application with Wide I/O memory on 2.5D-IC silicon interposer

Author

Chen-Chao Wang ; Hung-Hsiang Cheng ; Ming-Feng Chung ; Po-Chih Pan ; Chi-Tsung Chiu ; Chih-Pin Hung

Author_Institution

Electr. Lab., Adv. Semicond. Eng., Inc., Kaohsiung, Taiwan

fYear

2013

fDate

11-13 Nov. 2013

Firstpage

1

Lastpage

4

Abstract

A potential technology by silicon interposer enables high bandwidth and low power application processing devices of the future, because the demand of smart mobile products are driving for higher logic-to-memory bandwidth (BW) over 30 GB/s with lower power consumption and ultra-memory capacity. This paper presents a 2.5D-IC structure with silicon interposer to demonstrate electrical performances including signal integrity (SI) and power integrity (PI) by using WideIO memory interface. Of course, the accuracy of TSV has demonstrated by measurement as well.

Keywords

integrated circuit interconnections; low-power electronics; three-dimensional integrated circuits; 2.5D-IC silicon interposer; TSV technology; high bandwidth application; power integrity; signal integrity; wide IO memory interface; Analytical models; Couplings; Integrated circuit modeling; Noise; Silicon; Substrates; Through-silicon vias; 2.5D-IC; Through silicon via (TSV); WideIO; power integrity (PI); signal ntegrity (SI);

fLanguage

English

Publisher

ieee

Conference_Titel

CPMT Symposium Japan (ICSJ), 2013 IEEE 3rd

Conference_Location

Kyoto

Print_ISBN

978-1-4799-2718-0

Type

conf

DOI

10.1109/ICSJ.2013.6756088

Filename

6756088