A 15 b 5 MSample/s low-spurious CMOS ADC

This 15b CMOS ADC at 5MSample/s has four stages with 5, 5, 5, and 6b each. The number of bits resolved per stage is set higher to achieve the same resolution with less accurate components. Resolving more bits per stage greatly simplifies op amp design and reduces the initial capacitor matching requirement. Furthermore, residue amplifiers with low feedback factors are less sensitive to summing-node parasitics. The first two 5b stages are calibrated using the remaining part of the ADC. Two stages are selected for calibration. The gain ofthe 5b residue amplifier is set to 16 to make room for digital correction. After digital correction, the chip has an 18b output. Performance up to 16b level can be tested after removing 2 LSBs corrupted by digital processing. System partitioning and multi-stage calibration solve two fundamental problems of capacitor matching and finite opamp gain.