Mapping of IP cores to network-on-chip architectures based on communication task graphs

In this paper, we propose a scheme that automatically maps IP cores onto the network-on-chip architecture in SoC design. Our algorithm provides an efficient solution for satisfying design constraints, bandwidth of links, latency of communication paths, and average communication traffic. Two regular topologies, including mesh and torus, are assumed for the network. The X-Y routing and adaptive routing schemes are used to simulate the network for our algorithm. Experimental results show that our proposed algorithm decreases the required bandwidth of links compared to existing algorithms