Feedback driven high level synthesis for performance optimization

We propose a high level synthesis design flow in order to improve the circuit performance once the placement phase is done. We use a high level synthesis system known as automatic design instantiation (AUDI) to generate a register-transfer level (RTL) netlist. This netlist is then given to a Xilinx CAD tool for physical synthesis. Instead of routing the design right after the placement phase, we make use of the estimated interconnect delay, generate a guidance and give it to the high level synthesis system. The guidance consists of estimated timing information as well as instructions for producing a new netlist to improve the circuit performance. The design is finally routed on a satisfying design. This performance-driven high level synthesis framework yields significantly better results as compared with designs generated by a plain top-down design flow