A 40 Gb/s 8/spl times/8 ATM switch LSI using 0.25 /spl mu/m CMOS/SIMOX

The LSI has a re-routing banyan (RRB) type architecture that allows the construction of a nearly non-blocking network using a minimum number of switching elements. The 8/spl times/8 switch-chip architecture yields a 10/sup -8/ cell loss probability for a 0.9 offered load using 13 stages ofthe LSI in a 1 Tb/s RRB network. 0.25 /spl mu/m CMOS/SIMOX devices are used to increase chip bandwidth. The SSIs of the I/O and the 4:1 MUX circuit using CMOS/SIMOX exhibit 2.6 GHz operation, that is 1.4 times faster than bulk CMOS. In addition, a CMOS/SIMOX gate operated at 2.0 V dissipates 45 % less power than a bulk CMOS gate operated with the same propagation delay at 2.5 V. Thus, the CMOS/SIMOX device allows Gb/s interfaces as a part of a hundred-kilo-gate LSI with low power consumption. The circuit design reduces the number of gate fan-outs and wiring length. The design is especially effective in rising operating frequency owing to the fact that the source-drain (S/D) capacitance is one-third that of bulk CMOS.