SDH 10 Gb/s regenerator framer in 0.6 /spl mu/m CMOS

The requirement for higher bandwidth in the fixed network makes 10 Gb/s working in the SDH/SONET format an attractive alternative. Circuits performing the processing of SDH frames are needed. The framer is a part of a regenerator, the simplest SDH equipment. In addition to reshaping, the regenerator performs retiming and regenerating (3R) measurements on the status of the connection such as error rate, and communicates that information back to the operation and maintenance system. Multiplexers on the 2B level (l6:l) have a complexity that makes possible implementation in commercial technology. This gives a serial speed of 622 Mb/s at the framer-interface. CMOS has the power to operate at this I/O speed and with a 622 MHz internal clock. This facilitates a compact and cost-effective solution. Direct interfacing to STM-4/OC-12 (622 Mb/s) is also possible. The high clock frequency leads to a high degree of pipelining. The extra pipelining does not significantly affect the performance of the system since each pipeline only delays the signal as much as one extra foot of fibre.