RTL property checking technology based on ATPG and ILP

We propose a hybrid approach to RTL property checking that combines ATPG and ILP techniques. A special ATPG engine is designed for Boolean logic in our solver. And we use an ILP tool to solve the word-level arithmetic operator. This method is more unified and efficient than those using pure bit-level tools (such as grasp, chaff etc) or pure word-level tools (such as omega, CPLEX etc). The experiments on some public benchmarks and special circuit demonstrate the big advantage in time consumption of our approach