DocumentCode
3470575
Title
Non-serial Polyadic Dynamic Programming on a Data-Parallel Many-core Architecture
Author
Moazeni, M. ; Sarrafzadeh, Majid ; Bui, A.A.T.
Author_Institution
Comput. Sci. Dept., Univ. of California, Los Angeles, Los Angeles, CA, USA
fYear
2011
fDate
19-21 July 2011
Firstpage
52
Lastpage
55
Abstract
Dynamic Programming (DP) is a method for efficiently solving a broad range of search and optimization problems. As a result, techniques for managing large-scale DP problems are often critical to the performance of many applications. DP algorithms are often hard to parallelize. In this paper, we address the challenge of exploiting fine grain parallelism on a family of DP algorithms known as non-serial polyadic. We use an abstract formulation of non-serial polyadic DP, derived from RNA secondary structure prediction and matrix parenthesization approaches that are well-known and important problems from this family. We present a load balancing algorithm that achieves the best overall performance with this type of workload on many-core architectures. A divide-and-conquer approach previously used on multi-core architectures is compared against an iterative version. To evaluate these approaches, the algorithm was implemented on three NVIDIA GPUs using CUDA. We achieved up to 10 GFLOP/s performance and up to 228x speedup over the single-threaded CPU implementation. Moreover, the iterative approach results in up to 3.92x speedup over the divide-and-conquer approach.
Keywords
computer graphic equipment; coprocessors; divide and conquer methods; dynamic programming; iterative methods; macromolecules; matrix algebra; multiprocessing systems; resource allocation; CUDA; NVIDIA CPUs; RNA secondary structure prediction; data parallel many-core architecture; divide-and-conquer approach; fine grain parallelism; iterative approach; large-scale DP problems; load balancing algorithm; matrix parenthesization approaches; multicore architectures; nonserial polyadic dynamic programming; optimization problems; Computer architecture; Dynamic programming; Graphics processing unit; Iterative methods; Kernel; Load management; Parallel processing; Dynamic Programming; GPGPU; Many-core;
fLanguage
English
Publisher
ieee
Conference_Titel
Application Accelerators in High-Performance Computing (SAAHPC), 2011 Symposium on
Conference_Location
Knoxville, TN
Print_ISBN
978-1-4577-0635-6
Electronic_ISBN
978-0-7695-4448-9
Type
conf
DOI
10.1109/SAAHPC.2011.25
Filename
6031563
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