DocumentCode
3470749
Title
A delay metric for VLSI interconnect
Author
Du Zhong ; Zhiping, Wen ; Lixin, Yu
Author_Institution
Beijing Microelectron. Technol. Inst.
Volume
2
fYear
2005
fDate
24-0 Oct. 2005
Firstpage
1042
Lastpage
1046
Abstract
The Elmore delay RC metric, used widely to analysis interconnect delay, becomes ineffective for deep submicron technologies. Many interconnect delay models have been proposed by analyzing the moments of the impulse response, which are either computationally expensive or less accurate. In this paper, we present a new delay metric based on the first three moments of the impulse response, which has simple closed form expression and fast computation speed. The new metric is theoretically proven to be strictly less than the Elmore metric and is aprovably stable approximation. In the test for industrial nets, the average error is 3.8% for our model, less than other metrics
Keywords
VLSI; delay estimation; integrated circuit interconnections; transient response; Elmore delay RC metric; VLSI interconnect delays; impulse response; Capacitors; Circuit analysis; Circuit stability; Costs; Delay estimation; Integrated circuit interconnections; Microelectronics; System performance; Testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2005. ASICON 2005. 6th International Conference On
Conference_Location
Shanghai
Print_ISBN
0-7803-9210-8
Type
conf
DOI
10.1109/ICASIC.2005.1611479
Filename
1611479
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