1.38 cm/sup 2/ 550 MHz microprocessor with multimedia extensions

Author

Jain, A.K. ; Preston, R.P. ; Bannon, P.J. ; Bertone, M.S. ; Blake-Campos, R.P. ; Bouchard, G.A. ; Brasili, D.S. ; Carlson, D.A. ; Castelino, R.W. ; Clark, K.M. ; Kobayashi, S. ; Lilly, B.P. ; Mehta, S. ; Miller, B.S. ; Mueller, R.O. ; Olesin, A. ; Saito,

Author_Institution

Digital Equipment Corp., Hudson, MA, USA

fYear

1997

fDate

8-8 Feb. 1997

Firstpage

174

Lastpage

175

Abstract

This multi-media enhanced, quad-issue, 550MHz RISC microprocessor includes hardware for MPEG-II encode/decode. It delivers 30 frame/s DVD playback with stereo-quality audio. Extensions to the instruction set for motion video estimation provide an order of magnitude improvement in computational capability, enabling video teleconferencing at 30 frame/s. An on-chip cache controller supports module caches using pipelined burst SRAMs to deliver up to 3.2GB/s data. The chip supports built-in-self-test (BIST) and repair of on-chip caches to reduce test cost.

Keywords

built-in self test; cache storage; instruction sets; microprocessor chips; motion estimation; multimedia computing; reduced instruction set computing; teleconferencing; 3.2 GB/s; 550 MHz; DVD playback; MPEG-II encode/decode; RISC microprocessor; built-in-self-test; computational capability; instruction set; module caches; motion video estimation; multimedia extensions; on-chip cache controller; pipelined burst SRAMs; stereo-quality audio; video teleconferencing; Built-in self-test; Computer aided instruction; DVD; Decoding; Hardware; Microprocessors; Motion estimation; Reduced instruction set computing; Teleconferencing; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-3721-2

Type

conf

DOI

10.1109/ISSCC.1997.585322

Filename

585322