DocumentCode :
3470872
Title :
QUonG: A GPU-based HPC System Dedicated to LQCD Computing
Author :
Ammendola, Roberto ; Biagioni, Andrea ; Frezza, Ottorino ; Lo Cicero, Francesca ; Lonardo, Alessandro ; Paolucci, Pier Stanislao ; Rossetti, Davide ; Simula, Francesco ; Tosoratto, Laura ; Vicini, Piero
Author_Institution :
INFN, Sezione di Tor Vergata, Rome, Italy
fYear :
2011
fDate :
19-21 July 2011
Firstpage :
113
Lastpage :
122
Abstract :
QUonG is an INFN (Istituto Nazionale di Fisica Nucleare) initiative targeted to develop a high performance computing system dedicated to Lattice QCD computations. QUonG is a massively parallel computing platform that lever ages on commodity multi-core processors coupled with last generation GPUs. Its network mesh exploits the characteristics of LQCD algorithm for the design of a point-to-point, high performance, low latency 3-d torus network to interconnect the computing nodes. The network is built upon the APEnet+ project: it consists of an FPGA-based PCI Express board exposing six full bidirectional off-board links running at 34 Gbps each, and implementing RDMA protocol and an experimental direct network-to-GPU interface, enabling significant access latency reduction for inter-node data transfers. The final shape of a complete QUonG deployment is an assembly of standard 42U racks, each one capable of 60 TFlops/rack of peak performance, at a cost of 5 K€/TFlops and for an estimated power consumption of 25 KW/rack. A first QUonG system prototype is expected to be delivered at the end of the year 2011.
Keywords :
computer graphic equipment; coprocessors; field programmable gate arrays; lattice theory; multiprocessor interconnection networks; parallel architectures; quantum chromodynamics; FPGA-based PCI express board; GPU-based HPC system; LQCD computing; QUonG system prototype; RDMA protocol; high performance computing system; inter-node data transfers; multiprocessor interconnection networks; parallel computing platform; Computer architecture; Field programmable gate arrays; Graphics processing unit; Hardware; Lattices; Network interfaces; Transceivers; Computer networks; Multiprocessor interconnection networks; Parallel architectures;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Application Accelerators in High-Performance Computing (SAAHPC), 2011 Symposium on
Conference_Location :
Knoxville, TN
Print_ISBN :
978-1-4577-0635-6
Electronic_ISBN :
978-0-7695-4448-9
Type :
conf
DOI :
10.1109/SAAHPC.2011.15
Filename :
6031574
Link To Document :
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