A structural behavioural modelling approach for top-level analogue mixed-signal functional verifications

With ever-increasing complexity of SoC integration, top-level functional verification is imposed as one of the major challenges to the design community. Even with fast simulators being available, verifying top-level system behaviour with numerous control and operational modes is still impractical. This paper proposes a unified structural modelling approach for top-level functional verification of large-scale, complex analogue mixed-signal circuits with a number of control and operational modes. With basic circuit blocks being modelled using Verilog-A language, the complete system behaviour model is built structurally according to design hierarchy. The result is a behaviour model with pin-to-pin compatibility between the mathematical model and real circuit in the design database. This bottom-up model building procedure is automated by a novel Verilog-A netlisting tool. This approach is demonstrated with the model built for a high-frequency analogue front-end signal processing system used for optical disc control system. The effectiveness of this approach is shown model simulation results compared with transistor-level netlist simulation results with conventional circuit simulator (Spectre) and fast simulator (HSIM) respectively