Title :
Power distribution network design method based on frequency-dependent target impedance for jitter design of memory interface
Author :
Ikeda, Yasuhiro ; Toyama, Munehiro ; Muraoka, S. ; Uematsu, Yutaka ; Osaka, Hideki
Author_Institution :
Yokohama Res. Lab., Hitachi Ltd., Yokohama, Japan
Abstract :
This paper proposes a PDN design method using frequency-dependent target impedance considering frequency properties of jitter sensitivity of the IO buffer to power supply noise and switching current profile. We confirmed that this design and the resulting jitter of the I/O interface attributable to power supply noise meet the target value of less than 5 %UI.
Keywords :
distribution networks; power system harmonics; I/O interface; IO buffer; frequency-dependent target impedance; jitter design; memory interface; power distribution network design; power supply noise; switching current profile; Capacitors; Impedance; Integrated circuit modeling; Jitter; Noise; Power supplies; Switches; Power integrity; impedance; jitter;
Conference_Titel :
CPMT Symposium Japan (ICSJ), 2013 IEEE 3rd
Conference_Location :
Kyoto
Print_ISBN :
978-1-4799-2718-0
DOI :
10.1109/ICSJ.2013.6756114
