Design of an 11Gb/s CMOS Demultiplexer Using Redundant Multi-Valued Logic

This paper describes an 11 Gb/s CMOS demultiplexer (DEMUX) using redundant multi-valued logic (RMVL). The proposed circuit is receives serial binary data and is converted to parallel redundant multi-valued data. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented DEMUX is consisted of eight integrators. The DEMUX is designed with 0.35mum standard CMOS process. The validity and effectiveness are verified through HSPICE simulation. The DEMUX achieved the maximum data rate of 11 Gb/s and the average power consumption of 69.43mW. This circuit is expected to operate at higher speed than 11 Gb/s in the deep-submicron process of the high operating frequency