DocumentCode
3471132
Title
Development of single-chip multi-GB/s DRAMs
Author
Crisp, R. ; Donnelly, K. ; Moncayo, A. ; Perino, D. ; Zerbe, Jared
Author_Institution
Rambus Inc., Mountain View, CA, USA
fYear
1997
fDate
8-8 Feb. 1997
Firstpage
226
Lastpage
227
Abstract
Discusses improvement of current device jitter budget. A DRAM incorporating these improvements is expected to operate with 1.3Gb/s/pin signaling rate (650MHz clock rate) delivering 5.2GB/s from a 32b interface. Such a 64Mb density DRAM will exhibit a fill rate of 650times/s. Compared to an industry-standard 64M SDRAM operating at 66MHz with its 33times/s fill rate in a 2Mx32 organization, the ratio is 19.7:1.
Keywords
DRAM chips; clocks; integrated circuit design; jitter; 32 bit; 5.2 GB/s; 64 Mbit; 650 MHz; clock rate; device jitter budget; fill rate; signaling rate; single-chip multi-GB/s DRAMs; Bandwidth; Clocks; Costs; Delay; Frequency; Jitter; Pins; Random access memory; Throughput; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-3721-2
Type
conf
DOI
10.1109/ISSCC.1997.585351
Filename
585351
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