A 1.5 W single-chip MPEG2 MP@ML encoder with low power motion estimation and clocking

To produce practical single-chip MPEG2 encoder LSIs, it is important to reduce power dissipation and chip size. Low-efficiency pipeline-parallel processing designs for motion estimation (ME) require not only high clock frequency but also large power dissipation. Clock distribution is also a major factor in power dissipation. In conventional designs the power required for clock distribution depends not on the average performance but on the peak-performance required. This represents a waste of power. In response to this, adaptive search-area ME and demand clocking are used in a single-chip MPEG2 encoder LSI.