Latch-Based Clocking for Portable Low-Power Audio Applications

Author

Buergin, Felix ; Carbognani, Flavio ; Kaeslin, Hubert ; Felber, Norbert ; Fichtner, Wolfgang

Author_Institution

Integrated Syst. Lab., ETH Zurich

fYear

2006

fDate

23-26 Oct. 2006

Firstpage

1640

Lastpage

1642

Abstract

Two DSP algorithms for hearing aids have been integrated on silicon in a 0.18 mum CMOS process. Various level-sensitive two-phase clocking schemes have been evaluated in terms of energy efficiency. Actual measurements have confirmed energy savings of 64% over a recently published clock-gated single-edge-triggered one-phase implementation. Most of these improvements can be attributed to the thinning out of the clock tree made possible by the relaxed slew and skew constraints of level-sensitive clocking schemes

Keywords

CMOS integrated circuits; audio signal processing; clocks; hearing aids; silicon; 0.18 micron; CMOS process; DSP algorithms; Si; clock tree; energy efficiency; hearing aids; latch-based clocking; level-sensitive clocking schemes; portable low-power audio; two-phase clocking schemes; Auditory system; Clocks; Frequency; Hearing aids; Microphones; Noise cancellation; Noise reduction; Signal processing; Signal processing algorithms; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on

Conference_Location

Shanghai

Print_ISBN

1-4244-0160-7

Electronic_ISBN

1-4244-0161-5

Type

conf

DOI

10.1109/ICSICT.2006.306358

Filename

4098497