Doping profile design for substrate hot carrier reliability in deep submicron field effect transistors

The authors explore the impact of substrate hot carrier emission on the design of submicron FETs. Performance requirements increase the vertical field for decreasing feature size in the deep submicron regime. This in turn significantly enhances the degradation sensitivity to substrate hot carriers. Models that support reliability data show the relationship between device stability, and the location of the peak channel doping concentration with respect to the Si-SiO/sub 2/ interface. It is well established that increased surface concentration alone has the effect of increasing the rate of substrate hot carrier emission due to higher surface fields. These results show that an optimum design tradeoff of the apparently conflicting requirements of device stability, off-current and performance can be achieved by proper choice of doping peak location when key process tolerances are accounted for.<>