NBTI in dual gate oxide PMOSFETs

Author

Chaparala, Prasad ; Brisbin, Douglas ; Shi, James

Author_Institution

Adv. Process Technol. Dev., Nat. Semicond. Corp., Santa Clara, CA, USA

fYear

2003

fDate

24-25 April 2003

Firstpage

138

Lastpage

141

Abstract

In advanced analog and mixed signal applications, Negative Bias Temperature Instability (NBTI) in dual gate oxide (DGO) technologies poses significant challenges for process development and robust analog circuit design. In this paper, Vt mismatch shift due to NBTI in a cascode current mirror is examined. The impact of stress time, temperature, gate voltage, drain voltage, and annealing on NBTI degradation is investigated over a wide range of stress conditions. Proper process trade-offs must be made to reduce NBTI degradation while integrating a DGO module into a high performance CMOS core process.

Keywords

CMOS analogue integrated circuits; MOSFET; annealing; current mirrors; integrated circuit reliability; integrated circuit testing; 0.18 micron; 1000 hour; 85 to 150 C; DGO technologies; NBTI degradation; annealing; cascode current mirror; drain voltage; dual gate oxide PMOSFETs; gate voltage; high performance CMOS core process; negative bias temperature bistability; process development; process trade-offs; robust analog circuit design; stress time; threshold voltage mismatch shift; Analog circuits; Degradation; MOSFETs; Negative bias temperature instability; Niobium compounds; Robustness; Signal processing; Stress; Titanium compounds; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Plasma- and Process-Induced Damage, 2003 8th International Symposium

Print_ISBN

0-7803-7747-8

Type

conf

DOI

10.1109/PPID.2003.1200942

Filename

1200942