Sub-1-V CMOS Bandgap using Forward Body Bias of the PMOS Differential Pair for Reduction of the Threshold Voltages

A low voltage bandgap for 180 nm and 130 nm CMOS processes using standard threshold transistors and a forward body bias technique of the PMOS differential input pair is presented. The bandgap uses the current mode approach to generate a reference voltage below the silicon bandgap. The source-bulk-junction of the PMOS differential input is forward biased to lower the threshold voltage. The forward biasing switches on the parasitic bipolar comprising source, bulk and substrate, which reduces the bias current of the differential pair. This problem is considered during design and a new circuit is developed that compensates for the reduced bias current by adjusting the load current of the differential stage. The bandgap output voltage is 600 mV and consumes a supply current of only 9.5 muA