Title :
Deadlock avoidance and adaptive routing in interconnection networks
Author_Institution :
Fac. de Inf., Univ. Politecnica de Valencia, Spain
Abstract :
Networks of workstations are rapidly emerging as a cost effective alternative to parallel computers. Switch based interconnects with irregular topologies allow the wiring flexibility, scalability and incremental expansion capability required in this environment. The irregularity also makes routing and deadlock avoidance on such systems quite complicated. Current proposals avoid deadlock by removing cyclic dependencies between channels. As a consequence, many messages are routed following non minimal paths, therefore increasing latency and wasting resources. We describe a methodology for the design of adaptive routing algorithms for networks with irregular topology. The resulting algorithms allow messages to follow minimal paths in most cases, reducing message latency and balancing channel utilization. The proposed routing algorithms can be implemented simply by changing the routing tables and adding some links in parallel with existing links, taking advantage of spare switch ports. Alternatively, routing algorithms can be implemented by designing new switches that support virtual channels. Evaluation results show that the new routing algorithms are able to increase throughput by a factor of more than four for random traffic, also reducing latency
Keywords :
concurrency control; message passing; multiprocessor interconnection networks; workstations; adaptive routing; channel utilization; cyclic dependencies; deadlock avoidance; incremental expansion capability; interconnection networks; irregular topologies; irregular topology; message latency; message routing; networks of workstations; random traffic; spare switch ports; switch based interconnects; virtual channels; wiring flexibility; Algorithm design and analysis; Computer networks; Costs; Delay; Multiprocessor interconnection networks; Network topology; Routing; Switches; System recovery; Workstations;
Conference_Titel :
Parallel and Distributed Processing, 1998. PDP '98. Proceedings of the Sixth Euromicro Workshop on
Conference_Location :
Madrid
Print_ISBN :
0-8186-8332-5
DOI :
10.1109/EMPDP.1998.647220