DocumentCode
3472080
Title
A 1 V BiCMOS rail-to-rail amplifier with n-channel depletion-mode input-stage
Author
Griffith, R. ; Vyne, R. ; Dotson, R. ; Petty, T.
Author_Institution
Analog IC Div., Motorola Inc., Tempe, AZ, USA
fYear
1997
fDate
8-8 Feb. 1997
Firstpage
352
Lastpage
353
Abstract
This amplifier is fabricated on a SMARTMOS/sup TM/ flow with depletion-mode nMOS, vertical p-n-p, and high-frequency n-p-n transistors. Most techniques for achieving rail-to-rail input stage performance concentrate on the use of complementary bipolar or enhancement MOSFET devices to allow the amplifier common-mode range to include both supply rails. These techniques require a minimum supply voltage of 1.8 V for bipolar and 3 V for CMOS to allow a transition from sensing common mode voltages at ground when the p-n-p or pMOS pair is active, to sensing common-mode voltages at the positive supply when the n-p-n or nMOS pair is active. This amplifier uses a single pair of depletion-mode nMOS devices to allow low-voltage, rail-to-rail operation.
Keywords
BiCMOS analogue integrated circuits; differential amplifiers; operational amplifiers; 1 V; BiCMOS opamp; BiCMOS rail-to-rail amplifier; LV rail-to-rail operation; SMARTMOS process flow; body effect coefficient; common-mode range; depletion-mode nMOS; high-frequency n-p-n transistors; low-voltage rail-to-rail operation; n-channel depletion-mode input-stage; rail-to-rail input stage performance; vertical p-n-p transistors; 1f noise; BiCMOS integrated circuits; High power amplifiers; Low voltage; MOS devices; Mirrors; Operational amplifiers; Rail to rail amplifiers; Silicon; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-3721-2
Type
conf
DOI
10.1109/ISSCC.1997.585416
Filename
585416
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