A 12 b 28-channel trimless DAC

Author

Imamura, M. ; Kuwahara, K.

Author_Institution

Yokogawa Electr. Corp., Musashino, Japan

fYear

1997

fDate

8-8 Feb. 1997

Firstpage

384

Lastpage

385

Abstract

In ATE systems, the electronics for each pin employs more than ten 12 b DACs to provide dc level settings (i.e. pin driver rails, window comparator thresholds, programmable load currents, etc.). With increasing pin counts, a multi-channel chip structure becomes inevitable. A 12.7 b trimless DAC suitable for multi-channel applications is fabricated in a conventional double-metal 1.0 /spl mu/m CMOS process. The chip contains 28-channel DACs in 8.25/spl times/8.8mm/sup 2/ and consumes about 110 mW. The DAC utilizes a triple-rank architecture and binary-weighted transconductance (gm) to eliminate trimming and calibration.

Keywords

CMOS integrated circuits5609222; automatic test equipment; bipolar analogue integrated circuits; digital-analogue conversion; elemental semiconductors; silicon; timing circuits; 110 mW; 12 bit; ATE system; DC level setting; binary-weighted transconductance; double-metal CMOS chip; multichannel trimless DAC; pin electronics; triple-rank architecture; CMOS process; Calibration; Driver circuits; Feedback; Linearity; Operational amplifiers; Rails; Resistors; Switches; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-3721-2

Type

conf

DOI

10.1109/ISSCC.1997.585451

Filename

585451