A 20 MB/s data rate 2.5 V flash memory with current-controlled field erasing for 1 M cycle endurance

Author

Dallabora, M. ; Villa, C. ; Caser, F.T. ; Schippers, S. ; Sali, M. ; Ortolani, G. ; Geraci, A. ; Defendi, M. ; Cane, M. ; Bettini, L. ; Bartoli, S. ; Cantarelli, D. ; Bez, R.

Author_Institution

SGS-Thomson Microelectron., Agrate Brianza, Italy

fYear

1997

fDate

8-8 Feb. 1997

Firstpage

396

Lastpage

397

Abstract

Techniques to improve endurance and access time are applied to 2.5V high-density flash memory. A 4Mb flash product is used as a test vehicle for an erase method that extends the program/erase (P/E) endurance beyond 106 cycles. An embedded /spl mu/ROM controller with optimized algorithms (zero P/E array stress) minimizes erase time (parallel sector erase) and reduces testing time (BIST techniques). A 20MB/s read data throughput at 2.5V is obtained in OE synchronized data transfer mode. Dynamic redundancy enhances repair capability.

Keywords

EPROM; built-in self test; integrated circuit testing; life testing; redundancy; 2.5 V; 20 MB/s; 4 Mbit; BIST techniques; OE synchronized data transfer mode; access time; current-controlled field erasing; dynamic redundancy; endurance; erase method; erase time; flash memory; optimized algorithms; parallel sector erase; program/erase endurance; repair capability; Ear; Flash memory; Microelectronics; Nonvolatile memory; Paramagnetic resonance; Power supplies; Random access memory; Registers; Testing; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-3721-2

Type

conf

DOI

10.1109/ISSCC.1997.585456

Filename

585456