Two dimensionally inhomogeneous structure at gate electrode/gate insulator interface causing Fowler-Nordheim current deviation in nonvolatile memory

The gate electrode polycrystalline silicon (gate poly-Si)/gate insulator SiO/sub 2/ interface structure has been studied for obtaining reliable nonvolatile memory devices. The voltage deviation of Fowler-Nordheim tunneling current of the devices is discussed in terms of the SiO/sub 2/ surface roughness. High resolution scanning electron microscope (SEM) and atomic force microscope (AFM) measurements indicate that two dimensional nanometric oxide ridges are formed at the interface. It was found that a phosphorus dose below 2*10/sup 15/ cm/sup -2/, an annealing temperature below 900 degrees C, and the use of arsenic as a dopant resulted in the smooth SiO/sub 2/ surfaces. The reduction in the voltage deviation of the tunneling current is correspondingly obtained under these conditions. The oxide ridge growth can be explained by excess phosphorus distribution at grain boundaries and phosphorus-rich SiO/sub 2/ formation.<>