A 350 MHz 3.3 V 4 Mb SRAM fabricated in a 0.3 /spl mu/m CMOS process

Author

Braceras, G. ; Evans, D. ; Sousa, J. ; Conner, J.

Author_Institution

Microelectron. Div., IBM Corp., Essex Junction, VT, USA

fYear

1997

fDate

8-8 Feb. 1997

Firstpage

404

Lastpage

405

Abstract

A 35OMHz 4Mb SRAM chip in 2.5V 0.3/spl mu/m CMOS achieves a 4.1 ns flow-through access and uses self-timed, self-resetting, and low-signal swing circuits. The SRAM interfaces to LVTTL levels with a PECL clock, or to HSTL levels with either a single-ended or differential clock. The chip can be packaged in either 128k/spl times/36 or 256k/spl times/18 organizations and supports pipeline, dual-clock flowthrough, or register-latch timing protocols. A voltage regulator drives the internal power grid. High-speed circuits are used for the critical read performance path, and low-power static circuits are used in paths that do not gate chip performance.

Keywords

CMOS memory circuits; SRAM chips; clocks; timing; 0.3 micron; 3.3 V; 350 MHz; 4 Mbit; 4.1 ns; CMOS process; HSTL levels; LVTTL levels; PECL clock; SRAM; critical read performance path; differential clock; dual-clock flowthrough; flow-through access; high-speed circuits; internal power grid; low-power static circuits; low-signal swing circuits; register-latch timing protocols; self-resetting circuits; self-timed circuits; single-ended clock; Access protocols; CMOS process; Circuits; Clocks; Packaging; Pipelines; Random access memory; SRAM chips; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-3721-2

Type

conf

DOI

10.1109/ISSCC.1997.585460

Filename

585460