A 200 MHz RISC microprocessor with 128 kB on-chip caches

Author

Kever, W. ; Ziai, S. ; Hill, M. ; Weiss, D. ; Stackhouse, B.

Author_Institution

Hewlett-Packard Co., Fort Collins, CO, USA

fYear

1997

fDate

8-8 Feb. 1997

Firstpage

410

Lastpage

411

Abstract

The 32b PA-RISC 1.1 microprocessor features 64kB, two-way set-associative instruction and data caches on-chip, a controller for off-chip second-level cache of 256kB to 64MB, and an on-chip main memory and I/O controller. It operates up to 200MHz, with performance of 7.75 SPECint95 and 7.56 SPECfp95 in a 16OMHz system. The processor core is leveraged from a previous design, with circuit, fabrication process, and microarchitecture enhancements for improved performance and reduced power consumption. Circuit design allows high-frequency operation in the 0.5/spl mu/m, 3.3V CMOS process.

Keywords

CMOS digital integrated circuits; cache storage; microprocessor chips; pipeline processing; reduced instruction set computing; 0.5 micron; 128 kB; 200 MHz; 256 kB to 64 MB; 3.3 V; 32 bit; CMOS process; I/O controller; RISC microprocessor; high-frequency operation; microarchitecture enhancements; off-chip second-level cache; on-chip caches; on-chip main memory; power consumption; two-way set-associative instruction cache; Capacitance; Circuits; Clocks; Delay; Logic; Microprocessors; Pipelines; Random access memory; Reduced instruction set computing; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-3721-2

Type

conf

DOI

10.1109/ISSCC.1997.585462

Filename

585462