Title :
A 250 MHz 5 W RISC microprocessor with on-chip L2 cache controller
Author :
Reed, P. ; Alexander, M. ; Alvarez, J. ; Brauer, M. ; Chai-Chin Chao ; Croxton, C. ; Eisen, L. ; Toan Le ; Tai Ngo ; Nicoletta, C. ; Sanchez, H. ; Taylor, S. ; Vanderschaaf, N. ; Gerosa, G.
Author_Institution :
Somerset Design Center, Motorola Inc., Austin, TX, USA
Abstract :
This superscalar microprocessor is a 32b implementation of the PowerPC Architecture(TM) specification based on a micro-architecture designed for high performance and low power. Two instructions per cycle can be dispatched in this superscalar design. The processor includes dual 32kB 8-way instruction and data caches, a floating-point unit, two integer units, a branch unit, a load/store unit, and a system unit. An L2 tag and cache controller with a dedicated L2 bus interface are added to provide a low-cost L2 cache solution using commodity SRAMs for the data.
Keywords :
cache storage; floating point arithmetic; microprocessor chips; pipeline processing; reduced instruction set computing; 250 MHz; 32 bit; 5 W; PowerPC Architecture; RISC microprocessor; branch unit; bus interface; commodity SRAMs; data cache; floating-point unit; instruction cache; integer units; load/store unit; micro-architecture; on-chip L2 cache controller; superscalar microprocessor; system unit; Chaos; Clocks; Energy management; Frequency estimation; Microprocessors; Phase locked loops; Pipelines; Power system management; Reduced instruction set computing; Thermal management;
Conference_Titel :
Solid-State Circuits Conference, 1997. Digest of Technical Papers. 43rd ISSCC., 1997 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-3721-2
DOI :
10.1109/ISSCC.1997.585463
