Process Induced Layout Variability for Sub 90nm Technologies

For 65nm and beyond process technologies, identical transistors within a die can show large variations in on-current characteristics for different layouts. The proximity to the transistor of edges associated with different mask levels contribute to variability. Lithography proximity effects are dominant but other physical phenomena encountered with various process steps such as ion scattering, transient enhanced diffusion (TED) and mechanical strain engineering contribute to the variability. These effects can be modeled with TCAD. The results can be incorporated into the current SPICE models to enable designers to do more accurate simulations of the circuit on actual silicon