Increase the behavioral fault model accuracy using high-level synthesis information

Author

Brera, Marco ; Ferrandi, Fabrizio ; Sciuto, Donatella ; Fummi, Franco

Author_Institution

Dipt. di Elettronica e Inf., Politecnico di Milano, Italy

fYear

1999

fDate

36465

Firstpage

174

Lastpage

180

Abstract

This paper describes an approach for enhancing the effectiveness of behavioral test generation by considering high-level and logic synthesis information to increase the correlation between the behavioral fault model and the stuck-at-fault model. In particular we mainly consider two types of information: the mapping between high-level operators and RTL modules and the type of gate level implementation adopted by the RTL modules

Keywords

fault simulation; hardware description languages; high level synthesis; logic testing; HLS information; RTL modules; VHDL description; behavioral fault model; behavioral test generation; fault model accuracy improvement; gate level implementation; high-level operators; high-level synthesis information; logic synthesis information; stuck-at-fault model; Circuit faults; Circuit synthesis; Circuit testing; Consumer electronics; Electronic design automation and methodology; High level synthesis; Logic testing; Productivity; System-on-a-chip; Time to market;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1999. DFT '99. International Symposium on

Conference_Location

Albuquerque, NM

ISSN

1550-5774

Print_ISBN

0-7695-0325-x

Type

conf

DOI

10.1109/DFTVS.1999.802883

Filename

802883