DocumentCode
3472929
Title
A Scalable Design of RSA Crypto-coprocessor
Author
Gu, Yehua ; Zeng, Xiaoyang ; Han, Jun ; Ma, Yongxin ; Zhao, Jia
Author_Institution
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai
fYear
2006
fDate
23-26 Oct. 2006
Firstpage
1889
Lastpage
1892
Abstract
A scalable design of RSA crypto-coprocessor is presented in this paper, which supports variable keys up to 4096-bits. By analyzing and improving the modified multiple-word Montgomery multiplication algorithm, its pipeline architecture is optimized and critical path is greatly shortened. Meanwhile, its performance is much higher compared with previous work. Therefore, the proposed design is very suitable to the low-cost and high-performance RSA cryptosystem and can be easily implemented in VLSI technology
Keywords
VLSI; coprocessors; cryptography; pipeline processing; 4096 bit; Montgomery multiplication; RSA crypto-coprocessor; VLSI; critical path; pipeline architecture; Algorithm design and analysis; Application specific integrated circuits; Clocks; Delay; Internet; Partitioning algorithms; Pipelines; Public key cryptography; Security; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location
Shanghai
Print_ISBN
1-4244-0160-7
Electronic_ISBN
1-4244-0161-5
Type
conf
DOI
10.1109/ICSICT.2006.306498
Filename
4098572
Link To Document