Title :
SRAM delay fault modeling and test algorithm development
Author :
Huang, Rei-Fu ; Lai, Yan-Ting ; Chou, Yung-Fa ; Wu, Cheng-Wen
Author_Institution :
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
With the advent of deep-submicron VLSI technologies, the working speed of SRAM circuits has grown to a level that at-speed testing of SRAM has become an important issue. We present delay fault models for SRAM, i.e., the faults that affect the access time of the SRAM circuit. We also develop the test algorithm that detects these faults. The proposed SRAM delay-fault test algorithm has a complexity of 3N + 2k read/write operations, where N is the number of words and k is the word count in a row.
Keywords :
SRAM chips; VLSI; circuit CAD; circuit complexity; fault diagnosis; logic testing; system-on-chip; SRAM delay fault modeling; SRAM delay-fault test algorithm; complexity; deep-submicron VLSI technology; read/write operations; test algorithm development; Circuit faults; Circuit simulation; Circuit testing; Delay effects; Electrical fault detection; Fault detection; Logic testing; Random access memory; Read-write memory; Very large scale integration;
Conference_Titel :
Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific
Print_ISBN :
0-7803-8175-0
DOI :
10.1109/ASPDAC.2004.1337548
