FPGA ROUTING ARCHITECTURE OPTIMIZATION

Author

Tan, Jun ; Shen, Qiushi ; Chen, Yuanfeng ; Wang, Lingli ; Tong, Jiarong

Author_Institution

Dept. of Microelectron., Fudan Univ., Shanghai

fYear

2006

fDate

2006

Firstpage

1934

Lastpage

1936

Abstract

This paper presents a versatile SB model with 4 sides. It is so versatile that it can cover various kinds of 4-side SB( in the following paper, we use SB for short) architectures in a 2-D FPGA. Base on this model, a new SB structure with better routability in segmented architecture is proposed. Comparing with Subset, Wilton and Universal SBs, it improves 10.1%, 3.3% and 4.6% separately. In addition, we propose a new segment distribution method in segmented architecture, which can greatly reduce circuits delay. With the same technical parameter, 10.4% average improvement in critical path is gained in a new distribution method than in VPR´s when we use the universal SB

Keywords

delay circuits; field programmable gate arrays; network routing; FPGA; SB model; VPR; circuits delay; routing architecture optimization; segment distribution; segmented architecture; Application specific integrated circuits; Costs; Delay; Fabrication; Field programmable gate arrays; Laboratories; Microelectronics; Postal services; Routing; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on

Conference_Location

Shanghai

Print_ISBN

1-4244-0160-7

Electronic_ISBN

1-4244-0161-5

Type

conf

DOI

10.1109/ICSICT.2006.306533

Filename

4098585