Title :
FPGA Downloading Circuit Design and Implementation
Author :
Wang, Jian ; Chen, Li-Guang ; Lai, Jin-mei
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai
Abstract :
The most charming feature of FPGA is that it is post-fabricated, which means that user can design his own logic onto the chip without the need of tape out. So both design cycle and prototype cost can be greatly reduced. Once the bit file - which is a binary file representing the user designed logic s generated, it should be downloaded into the chip to realize the user logic. This paper deals with the way of loading the bit file into the FPGA chip, which has been taped out with SMIC 0.18mum CMOS process this year. Daisy chain and CRC check circuits are designed in this FPGA chip. We use MODELSIM to verify the design before and after the layout is generated. The area of downloading circuit is less than 3 percent of the whole chip
Keywords :
CMOS integrated circuits; field programmable gate arrays; integrated circuit design; logic design; 0.18 micron; CMOS process; CRC check circuits; Daisy chain; FPGA chip; FPGA downloading circuit design; bit file; CMOS logic circuits; Circuit synthesis; Clocks; Cyclic redundancy check; Field programmable gate arrays; Logic circuits; Logic design; Read-write memory; Switches; Writing;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on
Conference_Location :
Shanghai
Print_ISBN :
1-4244-0160-7
Electronic_ISBN :
1-4244-0161-5
DOI :
10.1109/ICSICT.2006.306538
