Energy/Performance/Area Tradeoffs in Nanometer FPGA Segmented Routing Architecture

Power is becoming a crucial design constraint for nanometer FPGAs. In this paper, we investigate the FPGA routing architectures on determining the best distribution of routing segment length considering energy, performance and area tradeoffs. We present evaluations on two new Vdd-programmable architectures and found that the best FPGA architecture uses Vdd-programmable clusters and Vdd-gateable interconnects. Compared to the baseline architecture, our best architecture reduces the minimal energy-delay-area product by 33.4%. Our experimental results also show that routing segment of length 3 gives the lowest energy consumption and the best energy-delay -area tradeoff, for all the evaluated architecture classes