DocumentCode
3473450
Title
Low power design using dual threshold voltage
Author
Ho, Yen-Te ; Hwang, Ting-Ting
Author_Institution
Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
fYear
2004
fDate
27-30 Jan. 2004
Firstpage
205
Lastpage
208
Abstract
We study the reduction of static power consumption by dual threshold voltage assignment. Our goal is, under given timing constraint, to select a maximum number of gates working at high-Vth such that the total power gain is maximized. We propose a maximum independent set based slack assignment algorithm to select gates for high-Vth. The results show that our assignment algorithm can achieve about 68% improvement as compared to results without using dual Vth.
Keywords
circuit optimisation; hardware description languages; logic design; logic gates; power consumption; dual threshold voltage assignment; independent set based slack assignment algorithm; low power design; static power consumption; CMOS process; Circuits; Computer science; Delay; Energy consumption; Fabrication; Sleep; Subthreshold current; Threshold voltage; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific
Print_ISBN
0-7803-8175-0
Type
conf
DOI
10.1109/ASPDAC.2004.1337566
Filename
1337566
Link To Document