• DocumentCode
    3473502
  • Title

    Testable design of GRM network with EXOR-tree for detecting stuck-at and bridging faults

  • Author

    Rahaman, Hafizur ; Das, Debesh K. ; Bhattacharya, Bhargab B.

  • Author_Institution
    Inf. Techol. Dept., B. E. Coll., Howrah, India
  • fYear
    2004
  • fDate
    27-30 Jan. 2004
  • Firstpage
    224
  • Lastpage
    229
  • Abstract
    A new testable realization of generalized Reed-Muller (GRM) expression with tree implementation of the EXOR-part is presented. This solves an open problem of designing an EXOR-tree based GRM network that admits a universal test set. For an n-variable function, the proposed design can be tested by (2n+8) test vectors, which are independent of the function and the circuit-under-test (CUT). Excepting a few intergate bridging faults in the EXOR-tree, it detects all other single bridging (both OR-and AND-type) and all single stuck-at faults. The EXOR-part is designed as a tree of depth (log2s +1), where s is the number of product terms in the given GRM expression. This reduces circuit delay significantly compared to cascaded EXOR-part. Further, for several benchmark circuits, the test set is found to be much smaller than those of the earlier tree-based designs.
  • Keywords
    Reed-Muller codes; design for testability; fault diagnosis; logic gates; logic testing; EXOR tree; benchmark circuits; bridging fault detection; circuit delay; circuit-under-test; generalized Reed-Muller expression; stuck-at fault detection; Benchmark testing; Boolean functions; Circuit faults; Circuit testing; Delay; Educational institutions; Electrical fault detection; Fault detection; Information technology; Logic testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific
  • Print_ISBN
    0-7803-8175-0
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2004.1337570
  • Filename
    1337570