Design and Implementation of Reconfigurable ECC Arithmetic Unit over GF(2m)

A reconfigurable ECC arithmetic unit new architecture is proposed in this paper based on the polynomial bases defined over GF(2^m). Based on the previous digit-serial multiplier, a new bit-parallel architecture for arbitrary irreducible polynomials multiplier is presented, which could eliminates module reduction circuit effectively. The new multiplier architecture could also be used together with an adder on square computing efficiently. Simulation results of FPGA indicate that the design can support most of point multiplication for different finite field´s degree m, which NIST recommended