DocumentCode
3473710
Title
On designing robust testable PLA for path delay faults
Author
Gupta, Bidyut ; Rajsuman, Rochit
Author_Institution
Southern Illinois University
Volume
2
fYear
1989
fDate
1989
Firstpage
999
Lastpage
1001
Keywords
Circuit faults; Circuit testing; Delay effects; Life testing; Logic circuits; Logic testing; Manufacturing; Programmable logic arrays; Propagation delay; Robustness;
fLanguage
English
Publisher
ieee
Conference_Titel
Signals, Systems and Computers, 1989. Twenty-Third Asilomar Conference on
Print_ISBN
0-929029-30-1
Type
conf
DOI
10.1109/ACSSC.1989.1201048
Filename
1201048
Link To Document