A CORDIC Demodulator Platform for Digital-IF Receiver

Author

Cui, Xiaoxin ; Yu, Dunshan ; Sheng, Shimin ; Cui, Xiaole

Author_Institution

Inst. of Microelectron., Peking Univ., Beijing

fYear

2006

fDate

23-26 Oct. 2006

Firstpage

2025

Lastpage

2027

Abstract

A reconfigurable CORDIC demodulator platform and design method for digital-IF receiver is presented. A 2-level FSK demodulator for family network is implemented and tested on that platform with Xilinx VirtexII XC2V1000-4FG256 FPGA. The 2-level FSK noncoherent detector is designed based on counting the zero crossing points using new noise elimination technique. Synchronization control information is extracted from the amplitude signal through setting protection parameters. The output BER is 0.01% for input SNR of 1dB with frequency offset of 0.1MHz

Keywords

demodulators; digital radio; field programmable gate arrays; frequency shift keying; radio receivers; signal processing; software radio; CORDIC demodulator platform; FPGA; FSK demodulator; FSK noncoherent detector; XC2V1000-4FG256; Xilinx VirtexII; digital-IF receiver; field programmable array; noise elimination technique; Bit error rate; Data mining; Demodulation; Design methodology; Detectors; Field programmable gate arrays; Frequency shift keying; Frequency synchronization; Protection; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on

Conference_Location

Shanghai

Print_ISBN

1-4244-0160-7

Electronic_ISBN

1-4244-0161-5

Type

conf

DOI

10.1109/ICSICT.2006.306582

Filename

4098613