Using C based logic synthesis to bridge the productivity gap

Digital circuits from software designs and formal executable specifications can be automatically synthesized using hardware compilation or ´C based logic synthesis´. Designs can be verified using that same formal specification and coupled with the increasing deployment of higher-level C based languages and IP reuse in hardware design and system codesign, C based logic synthesis is enabling new methodologies and levels of designer productivity. We discuss the rationale for such a synthesis approach, the required semantics and compilation technology and offer a contrast with RTL synthesis. Design examples are used to provide case studies of practical experience.