Design Of A Low-Swing On-Chip Interconnect Circuit

Author

Gao-jian, Cong ; Jia-yue, Qi

Author_Institution

Inst. of Microelectron., Tsinghua Univ., Beijing

fYear

2006

fDate

23-26 Oct. 2006

Firstpage

2091

Lastpage

2094

Abstract

Most of low-swing signaling circuits need a reference voltage, an extra timing control or special low-vt devices. We studied the SSDLC circuit, which need none of the three, working in a condition of 1.8V source voltage and 0.18um channel length. Problems come up and we modified the circuit. Simulation results show that proposed circuit 1 can decrease power-delay product by 37.2% compared with a CMOS buffer implemented with two inverters, and its layout is quite small. Circuit 2 is more complicated than circuit 1. Although has a larger layout, it decreases power-delay product by 62%

Keywords

CMOS integrated circuits; circuit layout; delay circuits; integrated circuit interconnections; power integrated circuits; system-on-chip; 0.18 micron; 1.8 V; CMOS buffer; SSDLC circuit; circuit layout; low swing circuit; on-chip interconnect circuit; power delay; Clocks; Driver circuits; Integrated circuit interconnections; Latches; MOSFETs; Power dissipation; Signal design; Threshold voltage; Voltage control; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 2006. ICSICT '06. 8th International Conference on

Conference_Location

Shanghai

Print_ISBN

1-4244-0160-7

Electronic_ISBN

1-4244-0161-5

Type

conf

DOI

10.1109/ICSICT.2006.306626

Filename

4098635