• DocumentCode
    3474257
  • Title

    Exploiting program execution phases to trade power and performance for media workload

  • Author

    Banerjee, Subhasis ; Surendra, G. ; Nandy, S.K.

  • Author_Institution
    Supercomput. Educ. & Res. Centre, Indian Inst. of Sci., Bangalore, India
  • fYear
    2004
  • fDate
    27-30 Jan. 2004
  • Firstpage
    387
  • Lastpage
    389
  • Abstract
    Processing streaming media comprises several program phases (often distinct) that are periodic and independent of application data. Here we characterize execution of such programs into execution phases based on their dynamic IPC (instruction per cycle) profile. We show that program execution of selected phases can be dynamically boosted by activating additional standby functional units which are otherwise powered down for saving energy. Through simulation we show that speedup ranging from 1.1 to 1.25 can be achieved while reducing the energy-delay product (EDP) for most of the media benchmarks evaluated. Additionally we show that artificially introduced stalls during phases of processor underutilization reduces power by around 2 to 4%.
  • Keywords
    instruction sets; microprocessor chips; multimedia systems; resource allocation; dynamic instruction per cycle; media workload; processor underutilization; program execution phase; Educational programs; Embedded system; High performance computing; Parallel processing; Power dissipation; Resource management; Runtime; Streaming media; Supercomputers; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific
  • Print_ISBN
    0-7803-8175-0
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2004.1337605
  • Filename
    1337605