Design and implementation of a high-speed and area-efficient viterbi decoder

A high-speed and area-efficient Viterbi decoder is presented in the paper, and a new survivor path structure including RAM blocks and trace-back decode circuit is proposed. The survivor path memory is consist of 4 single-port RAM blocks, which reduces the chip´s area comparing to the dual-port RAM structure; and a simple trace-back decoder circuit is implemented to get high speed. Only 2300 LEs are used in the Altera Stratix FPGA device to implement this design, and its speed is up to 163 MHz. The proposed Viterbi decoder can be introduced to the digital communication systems that need high speed such as DTV or HDTV broadcast