DocumentCode
3474382
Title
Tradeoff routing resource, runtime and quality in buffered routing
Author
Tang, Xiaoping ; Wong, Martin D F
Author_Institution
Cadence Design Syst., San Jose, CA, USA
fYear
2004
fDate
27-30 Jan. 2004
Firstpage
430
Lastpage
433
Abstract
With the wide use of hard macros and IP blocks in design, buffered routing (simultaneous routing and buffer insertion) becomes unavoidable. Routing resource allocation and distribution are serious concerns in buffered routing of deep submicron design. The capability of capturing the tradeoff between routing resource cost and signal delay is crucial in practice since the resource overuse of min-delay solution may cause congestion problem (congestion also means over-inserting buffers). However, many existing algorithms are mainly designed to minimize signal delay. Here, we first study the problem of minimizing the linear combination of delay and cost, and extend the graph-based algorithm in [X. Tang et al., (2001)] to solve it. We then show that a variant of the algorithm can solve other problems such as maximizing delay reduction to cost ratio, minimizing routing cost subject to a delay constraint, and minimizing delay subject to the cost not exceeding a given budget. We also develop a hierarchical approach to buffered routing construction for problems with large number of sinks to tradeoff solution quality and runtime.
Keywords
buffer storage; circuit analysis computing; graph theory; minimisation; network routing; resource allocation; buffered routing; graph-based algorithm; routing resource allocation; routing resource cost; signal delay; submicron design; Algorithm design and analysis; Costs; Delay lines; Integrated circuit interconnections; Resource management; Routing; Runtime; Signal design; System-on-a-chip; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific
Print_ISBN
0-7803-8175-0
Type
conf
DOI
10.1109/ASPDAC.2004.1337613
Filename
1337613
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