Design of Adiabatic SRAM Based on CTGAL Circuit

A new adiabatic logic circuit adopting two-phase power clocks - clocked transmission gate adiabatic logic (CTGAL) circuit was presented. CTGAL circuit was used to design a novel adiabatic SRAM, and its bootstrapped NMOS transistors and CMOS-latch structure could recover the charge of large switching capacitances on word-lines, write bit-lines, sense amplified lines and address decoders in a fully adiabatic manner. Using the parameters of TSMC 0.25mum CMOS device, the adiabatic SRAM based on CTGAL circuit was simulated by HSPICE. The simulation results indicated that this SRAM had correct logic function and the character of clearly low power