• DocumentCode
    3474541
  • Title

    A low-spurious low-power 12-bit 300MS/s DAC with 0.1mm2 in 0.18µm CMOS process

  • Author

    Wei-Te Lin ; Tai-Haur Kuo

  • Author_Institution
    Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
  • fYear
    2013
  • fDate
    3-5 June 2013
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    A low-spurious low-power 12-bit 300MS/s digital-to-analog converter (DAC) is proposed with only 0.1mm2 active area in a 0.18μm CMOS process. Measured performance achieves > 70dB spurious-free dynamic range (SFDR) in the whole Nyquist bandwidth and consumes 35mW. Two popular figure-of-merits (FoMs) are used to compare this design with other published DACs, with the proposed design performing best.
  • Keywords
    CMOS integrated circuits; digital-analogue conversion; low-power electronics; CMOS process; Nyquist bandwidth; active area; digital-to-analog converter; figure-of-merits; low-spurious low-power DAC; power 35 mW; size 0.18 mum; spurious-free dynamic range; word length 12 bit; Bandwidth; CMOS integrated circuits; Signal resolution; Universal Serial Bus; Binary-weight; Current-steering; DAC; DEM; Nyquist rate; SFDR;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices and Solid-State Circuits (EDSSC), 2013 IEEE International Conference of
  • Conference_Location
    Hong Kong
  • Type

    conf

  • DOI
    10.1109/EDSSC.2013.6628035
  • Filename
    6628035
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3474541